1. Field of the Invention
The present invention relates to transistor power amplifiers as may be used in, for example, a cell phone base station. In particular, the invention relates to a method and circuit for biasing the amplifier based on a frequency of an amplified signal to improve flatness and expansion properties of the amplifier's gain performance.
2. Description of Related Art
FIG. 10, a known power amplifier includes amplifying device Q1, an input matching (and biasing) network formed from capacitor C.sub.1 and inductor L.sub.1 and an output matching network formed from capacitor C.sub.2 and inductor L.sub.2. At lower frequencies, the input matching network and the output matching network are typically formed from discrete components. At higher frequencies (e.g., greater than 1,000 MHz), the input matching network and the output matching network are often formed from distributed capacitances, inductances and resistances as may be found in stripline, microstrip or similar circuits. Amplifying device Q1 is shown as an NPN transistor, but might also be a PNP transistor, an MOS transistor, or similar RF transistor. The amplifying device of FIG. 10 might also be a pair of matched transistors arranged in a balanced push pull circuit with appropriate couplers and matching circuits on the input and output.
The inherent resistance of inductor L.sub.2 combined with supply voltage V.sub.CC defines the slope and V.sub.C axis intercept of load line LL shown in FIG. 11. In general, the slope and V.sub.C axis intercept of load line LL is defined by the supply voltage and the total resistance between the collector and the supply voltage whether the resistance is produced by a discrete resistor, distributed resistance or inherent resistance of other components such as inductors. FIG. 11 depicts a graph of collector current I.sub.C as a function of voltage V.sub.C on the collector of transistor Q1, and the quiescent operating point of transistor Q1 is defined by a point on load line LL. For example, point A represents a quiescent operating point when voltage V.sub.3 is applied to the base of transistor Q1. In fact, FIG. 11 depicts six such transistor operating curves for base voltages from V.sub.1 through V.sub.6. Quiescent point A is achieved by setting bias voltage V.sub.BIAS to voltage V.sub.3 plus a small voltage drop that may occur across the inherent resistance of inductor L.sub.1 resulting from the direct (i.e., steady state) current into the base of transistor Q1.
Selection of quiescent point A creates a class A amplifier for input signal E.sub.I applied to the base of transistor Q1. In a class A amplifier, input signal E.sub.I applied to the base of transistor Q1 varies above and below the base bias voltage of V.sub.3. This momentarily deviates the transistor operating point above and below quiescent point A in a sinusoidal rhythm as depicted in FIG. 11. The voltage on the collector of transistor Q1 also varies sinusoidally and can be read off of the V.sub.C axis at the deviated transistor operating point. In a class A amplifier, the output signal waveform is a faithful reproduction with gain of the input signal waveform with little distortion (e.g., third harmonic distortion). However, if a class A amplfier is over driven by input signal E.sub.I, the amplifier can be driven into class AB operation. In a class A amplifier, transistor Q1 constantly dissipates power (i.e., V.sub.C I.sub.C) when operating at quiescent point A. This produces undesired heating of transistor Q1, a resulting undesired increase in an equivalent base spreading resistance, and a consequent reduction in the gain performance of the transistor at the high end of the frequency range.
Selection of quiescent point B creates a class B amplifier. In a class B amplifier, transistor Q1 is biased so that the quiescent current through transistor Q1 is zero. At such a bias point, transistor Q1 acts as a half wave rectifier. Only half of the sinusoidal waveform of input signal E.sub.I applied to the base of a class B amplifier actually appears on the collector of transistor Q1 (i.e., the output). The other half is "clipped". This produces significant distortion, particularly third harmonic distortion. However, in a class B amplifier, transistor Q1 dissipates no steady state power (i.e., V.sub.C I.sub.C) when operating at quiescent point B since collector current I.sub.C is zero.
Selection of quiescent point AB creates a class AB amplifier. In a class AB amplifier, the exact quiescent point AB can be selected by design requirements so as to limit the occurrence of third harmonic distortion to no more than that permitted by the system design requirements while at the same time minimizing the power dissipated in transistor Q1 consistent with the third harmonic distortion requirement. FIG. 11 depicts an output signal waveform with collector voltages varying about quiescent point AB where only a small portion of the waveform is "clipped", thus resulting in less distortion than would occur with a class B operation. Most large signal amplifiers designed for the cell phone industry use a class AB amplifier, in one form or another, because of the flexibility of the design to meet system distortion requirements while minimizing the dissipated power. It should be noted that a transistor biased to operate at quiescent point AB will operate as a class A amplifier if input signal E.sub.I is sufficiently small.
The distortion present in a large signal amplifier depends on how large the signal is. It is convenient, to measure the largeness of the signal as the signal power at the collector of transistor Q1, although other measures may be used. The signal power is the RMS (root mean squared) value of the alternating portion of the output signal, not the steady state power dissipated at the quiescent operating point. The output signal power passes through capacitor C.sub.2. The output signal power is also defined by input signal power multiplied by the power gain of transistor Q1.
FIG. 12 depicts a representative gain performance (e.g., power gain, but could be voltage gain or current gain) of the amplifier of FIG. 10. The amplifier gain varies between a minimum gain and a maximum gain when the operating frequency varies over a range of frequencies. To characterize the gain distribution, a gain flatness is defined to be one-half of the sum of the minimum gain plus the maximum gain.
FIG. 13 depicts the gain of a power amplifier with a collector current of transistor Q1 biased to be 70 milliamperes at three discrete frequencies (1,800 MHz and 1,840 MHz and 1,880 MHz) over a dynamic range of output signal powers that varies from 18.79 dBm to 37.71 dBm. Zero dBm is one milliwatt, and other output signal powers are expressed in dBm (i.e., decibels relative to one milliwatt). FIG. 13 illustrates gain expansion. At 1,800 MHz, the amplifier power gain varies from a little over 20 dB when the output signal power is set at 19 dBm to a maximum of 21 dB at an output signal power near 32 dBm and then drops to less than 17 dB at an output signal power near 37 dBm. A slightly different gain expansion can be observed in FIG. 13 for signal frequencies of 1,840 MHz and 1,880 MHz. FIG. 13 depicts that the amplifier gain measured over the three frequencies varies 2.5 dB (a measure of flatness) when operated with a signal providing a 23 dBm output signal power and varies 2.8 dB when operated with a signal providing a 32 dBm output signal power. This variation of the amplifier gain with increasing output signal power from the amplifier is referred to as a gain expansion. The gain even falls below 18 dB at the low frequency of 1,800 MHz.